1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to a semiconductor device in which the so-called latchup phenomena can be prevented.
2. Prior Art
As is well known, "latchup" refers to the formation of parasitic thyristors between the many transistor elements formed on a single semiconductor substrate. The turning on of such parasitic thyristors by, for example, noise near them prevents the transistor elements from functioning as desired and, thus, leads to erroneous operation in the semiconductor device. Generally, the higher the density and number of the transistor elements, the more prominent the occurrence of latchup. Latchup is therefore an especially serious problem in high integration semiconductor devices such as memory devices.
In prior art memory units, one technique for suppressing latchup when increasing the integration has been to form deep, passive isolation regions along the word lines. However, to increase the integration of such memory devices, it is also necessary to reduce the pitch with which the bit lines are arranged. This results in increased latchup between the transistor elements formed along adjacent bit lines. This also results in insufficient withstand voltage between adjacent bit lines.
The inventor has proposed, in Japanese Published Examined Patent Application No. 55-28218 (Japanese Pat. No. 1038742), to suppress latchup and increase the withstand voltage by the formation of additional shallow, passive isolation regions extending in a direction perpendicular to the direction of the above-mentioned deep passive isolation regions, thereby enclosing each transistor element. The reason for the shallowness of the additional regions is that the formation of deep regions would end up separating belts of so-called buried layers with highly dense impurities formed along the word lines into a plurality of divisions. In other words, this would cancel the principal purpose of the buried layers, that is, the reduction of the resistance along the word lines.
Use of shallow passive isolation regions would seemingly solve the problems of latchup and withstand voltage. In fact, however, there are often cases where latchup is not completely suppressed. The reason for this is believed to be that the pairs of deep passive isolation regions and the pairs of shallow passive regions may not completely enclose the transistor elements along their four sides.